1. Field of the Invention
This invention relates to MOSFET devices and more particularly to an improved process of manufacture.
2. Description of Related Art
A conventional Self-Aligned Contact (SAC) process uses a thick cap layer over polysilicon gate structures. The cap layer is composed silicon dioxide material for spacer and SAC contact etching back. The process window is a trade off with increased step height.
N/P MOS devices are formed before SAC formation, so the thermal cycling of devices increases, affecting the device margin.
U.S. Pat. No. 5,116,776 of Chan et al, "Method of Making a Stacked Capacitor for DRAM Cell" and U.S. Pat. No. 5,155,056 of Jeony-Gyoo for "Process for Formation of Cells Having Self-Aligned Capacitor Contacts, and Structure Thereof" show methods for making a DRAM device including a self-aligned contact for the capacitor.
Referring to FIGS. 1A-1F a conventional SAC process is illustrated by a series of cross sectional views of a device in the process of manufacture.
Referring to FIGS. 1A-1E a prior art process is illustrated by a series of cross sectional views of a device in accordance with a prior art process of manufacture.
FIG. 1A shows a process of prior art polysilicon gate definition and N- implant.
In FIG. 1A a prior art process includes a substrate 10 composed of lightly doped P-well or P-substrate silicon semiconductor material. The substrate 10 was processed to achieve the result shown in FIG. 1A. First, a silicon dioxide gate oxide layer 13 having a thickness of about 150 .ANG. is deposited. Then a polysilicon or polycide layer 12 is formed. Next, a silicon dioxide layer 14 is formed.
The polysilicon or polycide layer 12 and the silicon dioxide layer 14 are then patterned to form polysilicon gate structures 15 as shown in FIG. 1A by photolithography and etching.
Next N- dopant ions 17 composed of phosphorus (P.sup.31) or arsenic (As+) are implanted into N- regions 11 of substrate 10. The dopant is applied to provide counter-doping at a far higher level of doping than in the remainder of P-sub 10. The result is N- implanted regions 11, in the surface of the P- substrate 10 between the polysilicon or polycide layer gate structures 15.
FIG. 1B shows the result of prior art CVD silicon dioxide deposition. In FIG. 1B the result of the prior art deposition process is shown after CVD (chemical vapor deposition) of silicon dioxide (SiO.sub.2) to form a blanket spacer layer 16. The SiO.sub.2 layer 16 is preferably deposited in a CVD reactor.
FIG. 1C shows the result of prior art spacer etching (blank etching) N+doping. In particular, FIG. 1C shows spacers 18 formed from spacer oxide layer 16 as the result of an anisotropic blanket etching back process (without a mask) of RIE (reactive ion etching) with an oxide etcher during which regions 11 of substrate 10 are exposed between the spacers 16.
Next, dopant N+ ions 19 are implanted through the spaces between gate structures 15 into regions 20 and shallow N- regions 24 of substrate 10. The dopant applied is arsenic (As+.)
FIG. 1D shows the product of FIG. 1C after the result of prior art CVD silicon dioxide deposition and formation a SAC mask a CVD deposit of silicon dioxide (SiO.sub.2) layer 21. The SiO.sub.2 layer 21 is deposited in a CVD reactor. The CVD process employs a reactant gas(es) consisting of silane and oxygen O.sub.2.
Next, an SAC (Self Aligned Contact) mask for the CVD silicon dioxide SiO.sub.2 layer 21 is formed by depositing a blanket layer of photoresist, which is exposed and developed to produce the mask 22 leaving the central portion of the device in FIG. 1D exposed.
FIG. 1E shows the result of prior art formation of a SAC contact opening in the CVD silicon oxide layer 21. An etching process has patterned a portion of the silicon dioxide layer 21 exposed through mask 22 to open up a portion of the surface of N+ doped region 20. Plasma etching is employed using a conventional anisotropic oxide etchant. Then process steps follow comprising deposition of a polysilicon 2 layer, formation of a polysilicon 2 mask, and polysilicon 2 etching.
FIG. 1F shows the result of prior art polysilicon 2 deposition and polysilicon 2 definition for SAC (Self Aligned Contact) formation. The polysilicon 2 or polycide SAC contact 28 is deposited in contact with the surface of N+ doped region 20. The SAC contact 28 has been defined in the configuration shown.